1. Field of the Invention
The present invention relates to silicon oxide layers, their use in integrated circuit fabrication, and a method for forming a carbon doped silicon oxide layer.
2. Description of the Background Art
Integrated circuits have evolved into complex devices that can include millions of components (e. g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. The demands for greater circuit density necessitate a reduction in the dimensions of the integrated circuit components.
As the dimensions of the integrated circuit components are reduced (e.g., sub-micron dimensions), the materials used to fabricate such components contribute to their electrical performance. For example, low resistivity metal interconnects (e.g., copper and aluminum) provide conductive paths between the components on integrated circuits. Typically, the metal interconnects are electrically isolated from each other by an insulating material. When the distance between adjacent metal interconnects and/or the thickness of the insulating material has sub-micron dimensions, capacitive coupling potentially occurs between such interconnects. Capacitive coupling between adjacent metal interconnects may cause cross talk and/or resistance-capacitance (RC) delay which degrades the overall performance of the integrated circuit. In order to prevent capacitive coupling between adjacent metal interconnects, low dielectric constant (low k) insulating materials (e.g., dielectric constants less than about 4.5) are needed.
Therefore, a need exists in the art for low dielectric constant materials suitable for integrated circuit fabrication.
A method of forming a carbon-doped silicon oxide layer for use in integrated circuit fabrication is provided. In one embodiment, the carbon-doped silicon oxide layer is formed by applying an electric field to a gas mixture comprising an organosilane compound and an oxidizing gas.
The carbon-doped silicon oxide layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the carbon-doped silicon oxide layer is used as an intermetal dielectric layer. For such an embodiment, a preferred process sequence includes depositing the carbon-doped silicon oxide layer over conductive leads formed on a substrate.
In another integrated circuit fabrication process, the carbon-doped silicon oxide layer is incorporated into a damascene structure. For such an embodiment, a preferred process sequence includes depositing a first dielectric layer on a substrate. A carbon-doped silicon oxide layer is then formed on the first dielectric layer. Thereafter, the carbon-doped silicon oxide layer is patterned and etched to define contacts/vias therethrough. After the carbon-doped silicon oxide layer is patterned and etched, a second dielectric layer is deposited thereover. The second dielectric layer is then patterned and etched to define interconnects therethrough. The interconnects formed in the second dielectric layer are positioned over the contacts/vias formed in the carbon-doped silicon oxide layer. After the interconnects are formed the contacts/vias defined in the carbon-doped silicon oxide layer are etched through the first dielectric layer to the substrate surface. Thereafter, the damascene structure is completed by filling the interconnects and contacts/vias with a conductive material.